// -----------------------------------------------------------------------------
// Author : 3056710696@qq.com
// File   : tb_log.v
// Create : 2024-07-13 22:50:57
// Revise : 2024-07-14 22:06:42
// Editor : sublime text3, tab size (4)
// -----------------------------------------------------------------------------
`timescale 1ns / 1ns

module tb_log;
parameter PERIOD  = 10;

reg   				 clk                   ;
reg  				 rst_n                 ;
reg					 i_en				   ;
reg  	[31:0]		 data_in 			   ;
wire				 o_en 				   ;
wire	[31:0]		 data_out		 	   ;




initial
begin
clk                          = 0 ;
rst_n                        = 0 ;

end

initial
begin
   forever #(PERIOD/2)  clk =~clk; //clk的周期
end

initial
begin
   #(PERIOD*5) rst_n  =  1;  //复位信号
   #(PERIOD*6) i_en   =  1;  //输入使能信号
    		   data_in = 'd10;
   #(PERIOD*7) data_in = 100;
   #(PERIOD*8) data_in = 1000;
   #(PERIOD*9) data_in = 10000;
end





	log  inst_log (
			.clk      (clk),
			.rst_n    (rst_n),
			.i_en     (i_en),
			.data_in  (data_in),
			.o_en     (o_en),
			.data_out (data_out)
		);





endmodule

